The present invention relates generally to a semiconductor integrated circuit and, more particularly, to a semiconductor integrated circuit fabricated by a master slice approach, such as a gate array.
A master slice approach method is able to produce various semiconductor integrated circuits respectively having different logic functions and memory functions from a master wafer by modifying a wiring pattern formed on the master wafer. The master wafer comprises, for example, rows each of a plurality of basic cells each consisting of complementary MISFETs. A plurality of basic cells for an I/O buffer circuit, respectively corresponding to external terminals are arranged in the periphery of the semiconductor integrated circuit along the direction of arrangement of the external terminals.
Recent advancement in the function of the gate array type semiconductor integrated circuit device brought about an urgent demand for the further miniaturization and increase in the degree of integration of the circuit elements of the gate array.
A technique for the miniaturization of circuit elements and the augmentation of the degree of integration of the gate array is disclosed in Japanese Patent Laid-open No. 63-53948. According to this known technique, a rectangular basic cell for an input-output buffer circuit (hereinafter referred to as "I/O cell") disposed outside an internal cell array region in which a plurality of rows of basic cells are arranged at predetermined intervals along the direction of lines with wiring regions therebetween is divided into a basic cell for an input buffer circuit (hereinafter referred to as "input circuit cell") and a basic cell for an output buffer circuit (hereinafter referred to as "output circuit cell"), such input circuit cells and such output circuit cells are arranged alternately along the direction of arrangement of such I/O cells, and external terminals (hereinafter referred to as "bonding pads") are arranged around the I/O cell region in correspondence with the I/O cells.
This known technique divides an I/O cell forming region into input circuit cell forming regions and output circuit cell forming regions to decide the size of the input circuit cell forming regions without being restricted by the size of the output circuit cells. The size of the input circuit forming region is diminished by an area corresponding to a vacant space in which no circuit element is formed or an area saved by the miniaturization of the circuit elements.